This invention relates to a multiplication control system for multiplying a binary-coded multiplier and a binary-coded multiplicand.
The multiplication between binary-coded numbers is carried out by repeating an "add" operation a plurality of times, and the number of bits of the resultant product becomes larger than the numbers of bits of the multiplier and the multiplicand. In general, therefore, a "multiply" instruction requires an instruction executing period of time which is several times longer than that of an "add" or "subtract" instruction. At present, increasing use is being made of "multiply" instructions, not only in electronic computers for science, but also in electronic computers for business, and a variety of inconveniences have occurred due to the long time required for executing binary multiplication operations. Although various multiplication systems have heretofore been proposed, any of them has the disadvantage that the processing time is long. By way of example, a method of multiplication is known wherein the multiplier is processed a bit at a time. If the bit is "1," it is added to a multiplicand, while if the bit is "0," nothing is added. The resultant bit and the multiplier are shifted one digit. This operation is sequentially repeated for the respective bits. According to such a multiplication system, all the bits of the multiplier and the multiplicand must be sequentially processed in this manner. Therefore, the processing time remains fixed whatever the contents of the multiplier and the multiplicand may be. Disadvantageously, even when the number of significant bits is small, a long time for multiplication is required.